This disclosure relates to generating control signals for memory devices.
A memory device, such as a flash memory, can comprise a series of bit lines arranged in columns. Each bit line, in turn, is connected to a series of memory strings, and each memory string includes several memory locations, e.g., M1 . . . Mn, that correspond to bit locations. Each memory string has one end coupled to a corresponding bit line by a bit line selector, and another end coupled to a ground selector. Typically the bit line selector and the ground selector comprise transistors.
The columnar architecture of the bit lines and memory strings results in numerous parallel memory locations. Each memory location has in input terminal, e.g., a gate, and the memory locations are grouped in a row-like fashion by connecting the respective gates of the memory locations to a corresponding word lines.
To program a selected memory location in the flash memory, a memory string that includes the selected memory location is selected by coupling the memory string to a reference voltage, e.g., a ground voltage applied to the bit line, and the input to the memory location is coupled to a program voltage applied to the word line for a period of time sufficient to program the selected memory location. Another voltage of a lesser magnitude, e.g., a pass voltage, is applied to the word lines of memory locations in the memory string that are not to be programmed. Because the memory locations are grouped by rows defined by the word line, however, memory locations in parallel memory strings will also receive the program voltage and pass voltage. To prevent programming in the parallel strings, the corresponding bit line selectors and ground selectors are kept off. The resulting high impedance of the bit line selectors and the ground selectors allows the unselected memory strings to float in response the capacitive coupling of the world line voltages. The technique known as “channel boosting,” prevents the memory locations in the unselected string from being programmed.
To ensure that a memory string that shares the word line of the selected locations (e.g., a memory string on the same row as the selected memory string) is unselected, an unselect voltage, e.g., a supply voltage Vdd, is applied to the bit line to which that memory string is connected. The selected memory string, on the other hand, has a select voltage, e.g., a ground voltage. applied to a corresponding bit line. The memory strings defining other rows can have word line voltage at a reference value, e.g., ground or 0 volts, and can also have the gates of the bit line selectors at the reference value to ensure that the corresponding memory strings are unselected. On the other end, because the input of the bit line selector, e.g., a gate, on the row of the selected location also has the supply voltage applied, no forward bias is present in the bit line selector and the bit line selector is kept off. However, if the unselect voltage on the bit line is low, the bit line selector may be slightly forward biased and conduct. Such conduction can reduce the channel booting effect and cause inadvertent programming of other memory cells.